AMD FX-8150: Bulldozer on the bench table
We summarize briefly the main features of the FX-8150 CPU:
- 8 physical cores
- 3.6 GHz (up to 4.2 GHz in turbo mode)
- 3 Levels of Cache
- 8MB of unified last stage cache
- 4 HyperTransport Controllers
- Integrated dual-channel DDR3 controller
Main Exclusive Features
The Bulldozer architecture is the most innovative project designed to date after the introduction of K10 architecture common to Phenom and Athlon, because it exploits the cluster concept as a basic element for all CPUs made with CMT architecture (Cluster Multi-Threading). Moreover Bulldozer is conceptually the union of 2 independent dual-core modules linked by a second-level cache, but also from a shared floating point unit, that can operate as a single unit with 256-bit or operate separately and simultaneously as two independent 128-bit units. Each Bulldozer module contains a second level L2 cache of 2 MB shared between the two cores. The diagram below illustrates the concept.
It is clear that AMD has characterized the Bulldozer architecture by a highly scalable and future-oriented solutions that will evolve into increasingly more cores. It's the same principle of the Cloud and the clustering (let me use the term) through independent modules whose flow and operations in terms of efficiency has been greatly improved in order to avoid data redundancy. The optimization / efficiency of flows and the operations of a single Bulldozer block led, according to AMD, to an 80% efficiency compared to an architecture consisting of 2 separate cores with shared resources, with lower power consumption . This is a major achievement that brought bulldozers to reach a maximum operating frequency of 4.2 GHz in turbo mode. We propose for comparison the scheme with the comparative of Bulldozer and Intel i5/i7 architecture: the differences are considerable.
Recall that a more in-depth review of Bulldozer is available on our website with the article: AMD Bulldozer at debut.
Before continuing, a little update on the statistics of the Bulldozer die, for which, as stated also by AMD, were given incorrect data.
AMD said it integrated about 2.2 billion transistors in a die of 315 mm 2.After the launch of Interlagos, this value was reduced to only 1.2 billion, almost half. In relation to Llano, which uses the same 32nm manufacturing process, Bulldozer seems to be much less "dense". This probably can be explained by the presence of a greater amount of cache that takes up more surface area compared to the processing units of Llano GPU. Comparing with the data relating to Intel, the 32m HKMG SOI process seems to require a greater amount of space than the 32nm Bulk HKMG process. The comparison with Thuban leaves some doubt here, since it has a spatial density slightly less than the 45nm manufacturing process.
Note: some sources report a number equal to 995 million for Sandy Bridge transistors instead of 1.16 billions, but unfortunately there is no official figure on.
We conclude this section with a comparison of the AMD FX CPUs now available: